Technology advances allows for the creation of larger and more complex designs. This poses new challenges, including efforts to balance verification completeness with minimization of overall ...

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...

Atrenta’s Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs.

As outlined in a prior post, new advances in formal and multi-engine technology (like Incisive Enterprise Verifier or "IEV") enables users to do complete verification of design IP using only ...

Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these ...